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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. ad9740 * 10-bit, 165 msps txdac d/a converters * protected by u.s. patent numbers 5568145, 5689257, and 5703519. features high performance member of pin compatible txdac product family excellent spurious-free dynamic range performance snr @ 5 mhz output, 125 msps: 65 db twos complement or straight binary data format differential current outputs: 2 ma to 20 ma power dissipation: 135 mw @ 3.3 v power-down mode: 15 mw @ 3.3 v on-chip 1.2 v reference cmos compatible digital interface 28-lead soic, 28-lead tssop, and 32-lead lfcsp packages edge-triggered latches applications wideband communication transmit channel: direct if base stations wireless local loop digital radio link direct digital synthesis (dds) instrumentation functional block diagram 150pf + 1.2v ref avdd acom reflo current source array 3.3v segmented switches lsb switch refio fs adj dvdd dcom clock 3.3v r set 0.1 f clock iouta ioutb latches ad9740 sleep digital data inputs (db9db0) mode general description the ad9740 is a 10-bit resolution, wideband, third generation member of the txdac series of high performance, low power cmos digital-to-analog converters (dacs). the txdac family, consisting of pin compatible 8-, 10-, 12-, and 14-bit dacs, is specifically optimized for the transmit signal path of communica- tion systems. all of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. the ad9740 offers exceptional ac and dc performance while supporting update rates up to 165 msps. the ad9740 s low power dissipation makes it well suited for portable and low power applications. its power dissipation can be further reduced to a mere 60 mw with a slight degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 15 mw. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge- triggered input latches and a 1.2 v temperature compensated band gap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support 3 v cmos logic families. product highlights 1. the ad9740 is the 10-bit member of the pin compatible txdac family, which offers excellent inl and dnl performance. 2. data input supports twos complement or straight binary data coding. 3. high speed, single-ended cmos clock input supports 165 msps conversion rate. 4. low power: complete cmos dac function operates on 135 mw from a 2.7 v to 3.6 v single supply. the dac full- scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference: the ad9740 includes a 1.2 v temperature compensated band gap voltage reference. 6. industry-standard 28-lead soic, 28-lead tssop, and 32- lead lfcsp packages.
rev. a ? ad9740?pecifications (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) dc specifications parameter min typ max unit resolution 10 bits dc accuracy 1 integral linearity error (inl) C 0.7 0.15 +0.7 lsb differential nonlinearity (dnl) C 0.5 0.12 +0.5 lsb analog output offset error C 0.02 +0.02 % of fsr gain error (without internal reference) C 2 0.1 +2 % of fsr gain error (with internal reference) C 2 0.1 +2 % of fsr full-scale output current 2 220ma output compliance range C 1 +1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance (ext. reference) 1 m w small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 2.7 3.3 3.6 v dvdd 2.7 3.3 3.6 v clkvdd 2.7 3.3 3.6 v analog supply current (i avdd )333 6ma digital supply current (i dvdd ) 4 89ma clock supply current (i clkvdd ) 56ma supply current sleep mode (i avdd ) 56ma power dissipation 4 135 145 mw power dissipation 5 145 mw power supply rejection ratio avdd 6 C 1+ 1% of fsr/v power supply rejection ratio dvdd 6 C 0.04 +0.04 % of fsr/v operating range C 40 +85 c notes 1 measured at iouta, driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 times the i ref current. 3 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 4 measured at f clock = 25 msps and f out = 1 mhz. 5 measured as unbuffered voltage output with i outfs = 20 ma and 50 w r load at iouta and ioutb, f clock = 100 msps and f out = 40 mhz. 6 5% power supply variation. specifications subject to change without notice.
rev. a ad9740 ? dynamic specifications parameter min typ max unit dynamic performance maximum output update rate (f clock ) 165 msps output settling time (t st ) (to 0.1%) 1 11 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 2 50 pa/ hz output noise (i outfs = 2 ma) 2 30 pa/ hz noise spectral density 3 C 143 dbm/hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output 71 79 dbc C 6 dbfs output 75 dbc C 12 dbfs output 67 dbc C 18 dbfs output 61 dbc f clock = 65 msps; f out = 1.00 mhz 84 dbc f clock = 65 msps; f out = 2.51 mhz 80 dbc f clock = 65 msps; f out = 10 mhz 78 dbc f clock = 65 msps; f out = 15 mhz 76 dbc f clock = 65 msps; f out = 25 mhz 75 dbc f clock = 165 msps; f out = 21 mhz 70 dbc f clock = 165 msps; f out = 41 mhz 60 dbc spurious-free dynamic range within a window f clock = 25 msps; f out = 1.00 mhz; 2 mhz span 80 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 90 dbc f clock = 65 msps; f out = 5.03 mhz; 2.5 mhz span 90 dbc f clock = 125 msps; f out = 5.04 mhz; 4 mhz span 90 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz C 79 C 71 dbc f clock = 50 msps; f out = 2.00 mhz C 77 dbc f clock = 65 msps; f out = 2.00 mhz C 77 dbc f clock = 125 msps; f out = 2.00 mhz C 77 dbc signal-to-noise ratio f clock = 65 msps; f out = 5 mhz; i outfs = 20 ma 70 db f clock = 65 msps; f out = 5 mhz; i outfs = 5 ma 81 db f clock = 125 msps; f out = 5 mhz; i outfs = 20 ma 65 db f clock = 125 msps; f out = 5 mhz; i outfs = 5 ma 76 db f clock = 165 msps; f out = 5 mhz; i outfs = 20 ma 64 db f clock = 165 msps; f out = 5 mhz; i outfs = 5 ma 71 db multitone power ratio (8 tones at 400 khz spacing) f clock = 78 msps; f out = 15.0 mhz to 18.2 mhz 0 dbfs output 65 dbc C 6 dbfs output 66 dbc C 12 dbfs output 60 dbc C 18 dbfs output 55 dbc notes 1 measured single-ended into 50 w load. 2 output noise is measured with a full-scale output set to 20 ma with no conversion activity. it is a measure of the thermal nois e only. 3 noise spectral density is the average noise power normalized to a 1 hz bandwidth, with the dac converting and producing an outp ut tone. specifications subject to change without notice. (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, differential transformer coupled output, 50 doubly terminated, unless otherwise noted.)
rev. a ? ad9740 (t min to t max , avdd = 3.3 v, dvdd = 3.3 v, clkvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted.) digital specifications parameter min typ max unit digital inputs 1 logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?0 +10 ? logic 0 current ?0 +10 ? input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw ) 1.5 ns clk inputs 2 input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v notes 1 includes clock pin on soic/tssop packages and clk+ pin on lfcsp package in single-ended clock input mode. 2 applicable to clk+ and clk?inputs when configured for differential or pecl clock input mode. specifications subject to change without notice. 0.1% 0.1% t s t h t lpw t pd t st db0?b9 clock iouta or ioutb figure 1. timing diagram
rev. a ad9740 ? ordering guide model temperature range package description package options * ad9740ar ?0? to +85? 28-lead 300-mil soic r-28 ad9740arrl ?0? to +85? 28-lead 300-mil soic r-28 ad9740aru ?0? to +85? 28-lead tssop ru-28 ad9740arurl7 ?0? to +85? 28-lead tssop ru-28 AD9740ACP ?0? to +85? 32-lead lfcsp cp-32 AD9740ACPrl7 ?0? to +85? 32-lead lfcsp cp-32 ad9740-eb evaluation board (soic) AD9740ACP-pcb evaluation board (lfcsp) * r = small outline ic; ru = thin shrink small outline package; cp = lead frame chip scale package caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9740 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. thermal characteristics * thermal resistance 28-lead 300-mil soic ja = 55.9?/w 28-lead tssop ja = 67.7?/w 32-lead lfcsp ja = 32.5?/w * thermal impedance measurements were taken on a 4-layer board in still air, in accordance with eia/jesd51-7. absolute maximum ratings * with parameter respect to min max unit avdd acom ?.3 +3.9 v dvdd dcom ?.3 +3.9 v clkvdd clkcom ?.3 +3.9 v acom dcom ?.3 +0.3 v acom clkcom ?.3 +0.3 v dcom clkcom ?.3 +0.3 v avdd dvdd ?.9 +3.9 v avdd clkvdd ?.9 +3.9 v dvdd clkvdd ?.9 +3.9 v clock, sleep dcom ?.3 dvdd + 0.3 v digital inputs, mode dcom ?.3 dvdd + 0.3 v iouta, ioutb acom ?.0 avdd + 0.3 v refio, reflo, fsadj acom ?.3 avdd + 0.3 v clk+, clk? cmode clkcom ?.3 clkvdd + 0.3 v junction temperature 150 ? storage temperature ?5 +150 ? lead temperature (10 sec) 300 ? * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability.
rev. a ? ad9740 pin configuration pin function descriptions soic / tssop lfcsp pin no. pin no. mnemonic description 12 7 db9 most significant data bit (msb). 2? 28?2, 1, 2, 4 db8?b1 data bits 8?. 10 5 db0 least significant data bit (lsb). 11?4 6? nc no internal connection. 15 25 sleep power-down control input. active high. contains active pull-down circuit; it may be left unterminated if not used. 16 n/a reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 23 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal refer ence activated (i.e., tie reflo to acom). requires 0.1 ? capacitor to acom when internal reference activated. 18 24 fs adj full-scale current output adjust. 19 n/a nc no internal connection. 20 19, 22 acom analog common. 21 20 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 21 iouta dac current output. full-scale current when all data bits are 1s. 23 n/a reserved reserved. do not connect to common or supply. 24 17, 18 avdd analog supply voltage (3.3 v). 25 16 mode selects input data format. connect to dcom for straight binary, dvdd for twos complement. n/a 15 cmode clock mode selection. connect to clkcom for single-ended clock receiver (drive clk+ and float clk?. connect to clkvdd for differential re ceiver. float for pecl receiver (terminations on-chip). 26 10, 26 dcom digital common. 27 3 dvdd digital supply voltage (3.3 v) 28 n/a clock clock input. data latched on positive edge of clock. n/a 12 clk+ differential clock input. n/a 13 clk differential clock input. n/a 11 clkvdd clock supply voltage (3.3 v). n/a 14 clkcom clock common. 28-lead soic and tssop 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9740 nc = no connect db8 db7 db6 db5 db4 db3 db2 db1 nc clock dvdd dcom mode avdd reserved iouta ioutb acom nc fs adj refio reflo sleep (m sb) db9 nc nc nc db0 32-lead lfcsp pin 1 indicator top view 24 fs adj 23 refio 22 acom 21 iouta db3 1 db2 2 dvdd 3 32 db4 20 ioutb 19 acom 18 avdd 17 avdd nc 9 dcom 10 clkvdd 11 clk 12 clk 13 clkcom 14 cmode 15 mode 16 db1 4 db0 5 nc 6 nc 7 nc 8 31 db5 30 db6 29 db7 27 db9 (msb) 26 dcom 25 sleep ad9740 28 db8 nc = no connect
rev. a ad9740 ? definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called the offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is ex pected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range containing multiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. 1.2v ref avdd refloreflo pmos current source array 3.3v segmented switches for db9?b1 lsb switch refio fs adj dvdd dcom clock 3.3v r set 2k 0.1 f dvdd dcom iouta ioutb ad9740 sleep 50 retimed clock output * latches digital data tektronix awg-2021 with option 4 lecroy 9210 pulse generator clock output 50 50 rohde & schwarz fsea30 spectrum analyzer mini-circuits t1?t * awg2021 clock retimed so that the digital data transitions on falling edge of 50% duty cycle clock. 150pf mode figure 2. basic ac characterization test setup (soic/tssop packages)
rev. a ? ad9740?ypical performance characteristics 95 90 85 80 75 70 65 60 010 f out (mhz) sfdr (dbc) 100 55 50 45 65msps 125msps 125msps (lfcsp) 165msps 165msps (lfcsp) tpc 1. sfdr vs. f out @ 0 dbfs 060 10 45 50 55 60 65 70 75 80 85 90 95 f out (mhz) sfdr (dbc) 40 30 20 50 ?2dbfs ?dbfs 0dbfs tpc 4. sfdr vs. f out @ 165 msps ?0 ?5 ?5 ?0 ? 0 45 55 65 75 85 95 a out (mhz) sfdr (dbc) 165msps 125msps 65msps tpc 7. single-tone sfdr vs. a out @ f out = f clock /5 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 f out (mhz) sfdr (dbc) ?2dbfs ?dbfs 0dbfs tpc 2. sfdr vs. f out @ 65 msps 05 25 10 15 20 45 50 55 60 65 70 75 80 85 90 95 20ma 10ma 5ma f out (mhz) sfdr (dbc) tpc 5. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs 65 105 45 125 145 165 50 55 60 65 75 80 f clock ( msps) snr (db) 25 70 20ma 10ma 5ma tpc 8. snr vs. f clock and i outfs @ f out = 5 mhz and 0 dbfs 05 45 10 15 35 45 50 55 60 65 70 75 80 85 90 95 0dbfs ?dbfs ?2dbfs f out (mhz) sfdr (dbc) 40 30 20 25 tpc 3. sfdr vs. f out @ 125 msps 0 ? ?5 ?0 ?5 ?0 45 55 65 75 85 95 a out (dbfs) sfdr (dbc) 165msps 125msps 65msps tpc 6. single-tone sfdr vs. a out @ f out = f clock /11 45 50 55 60 65 70 75 80 85 90 95 a out (dbfs) sfdr (dbc) 0 ? ?0 ?5 ?0 ?5 78msps 165msps 125msps 65msps tpc 9. dual-tone imd vs. a out @ f out = f clock /7
rev. a ad9740 ? 0 256 512 768 1024 ?.25 ?.15 ?.05 0.05 0.15 0.25 code error (lsb) tpc 10. typical inl 16 26 11 16 21 ?00 frequency (mhz) magnitude (dbm) 31 f clock = 78msps f out = 15.0mhz sfdr = 77dbc amplitude = 0dbfs 36 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 tpc 13. single-tone sfdr 0 256 512 768 1024 ?.25 ?.15 ?.05 0.05 0.15 0.25 code error (lsb) tpc 11. typical dnl 16 26 11 16 21 ?00 frequency (mhz) magnitude (dbm) 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz sfdr = 77dbc amplitude = 0dbfs 36 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 tpc 14. dual-tone sfdr ?0 ?0 60 02040 50 55 60 65 70 75 80 85 90 4mhz 19mhz 34mhz temperature ( c) sfdr (dbc) 80 49mhz tpc 12. sfdr vs. temperature @ 165 msps, 0 dbfs 16 26 11 16 21 ?00 frequency (mhz) magnitude (dbm) 31 f clock = 78msps f out1 = 15.0mhz f out2 = 15.4mhz f out3 = 15.8mhz f out4 = 16.2mhz sfdr = 72dbc amplitude = 0dbfs 36 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 tpc 15. four-tone sfdr
rev. a ?0 ad9740 functional description figure 3 shows a simplified block diagram of the ad9740. the ad9740 consists of a dac, digital control logic, and full-scale output current control. the dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted fractions of the middle bits current sources. implement- ing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dac s high output impedance (i.e., >100 k w ). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the switches are based on the architecture that was pioneered in the ad9764 family, with further refinements to reduce distortion contributed by the switching transient. this switch architecture also reduces vari- ous timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9740 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 v to 3.6 v range. the digital section, which is capable of operating at a clock rate of up to 165 msps, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.2 v band gap voltage reference, and a reference control amplifier. the dac full-scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set , connected to the full-scale adjust (fs adj) pin. the external resistor, in combination with both the refer- ence control amplifier and voltage reference, v refio , sets the reference current i ref , which is replicated to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is 32 times i ref . digital data inputs (db9?b0) 150pf + 1.2v ref avdd acom reflo pmos current source array 3.3v segmented switches for db9?b1 lsb switch refio fs adj dvdd dcom clock 3.3v r set 2k 0.1 f iouta ioutb ad9740 sleep latches i ref v refio clock ioutb iouta r load 50 v outb v outa r load 50 v diff = v outa ?v outb mode figure 3. simplified block diagram (soic/tssop packages) reference operation the ad9740 contains an internal 1.2 v band gap reference. the internal reference can be disabled by raising reflo to avdd. it can also be easily overridden by an external reference with no effect on performance. refio serves as either an input or an output depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor and connect reflo to acom via a resistance less than 5 w . the internal reference voltage will be present at refio. if the voltage at refio is to be used anywhere else in the circuit, an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in figure 4. 150pf +1.2v ref avdd reflo current source array 3.3v refio fs adj 2k 0.1 f ad9740 additional load optional external ref buffer figure 4. internal reference configuration an external reference can be applied to refio, as shown in figure 5. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal refer- ence is overridden, and the relatively high input impedance of refio minimizes any loading of the external reference. 150pf +1.2v ref avdd reflo current source array refio fs adj r set ad9740 external ref i ref = v refio /r set avdd reference control amplifier v refio 3.3v figure 5. external reference configuration
rev. a ad9740 ?1 reference control amplifier the ad9740 contains a control amplifier that is used to regu- late the full-scale output current, i outfs . the control amplifier is configured as a v-i converter, as shown in figure 4, so that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied to the segmented current sources with the proper scale factor to set i outfs , as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting i ref between 62.5 a and 625 a. the wide adjustment span of i outfs pro vides several benefits. the first relates directly to the power dissipation of the ad9740, which is proportional to i outfs (refer to the power dissipation section). the second relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 500 khz and can be used for low frequency small signal multiplying applications. dac transfer function both dacs in the ad9740 provide complementary current outputs, iouta and ioutb. iouta provides a near full- scale current output, i outfs , when all bits are high (i.e., dac code = 1023) while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as iouta dac code i outfs = () / 1024 (1) ioutb dac code i outfs = () 1023 1024 ?/ (2) where dac code = 0 to 1023 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage, v refio , and external resistor, r set . it can be expressed as ii outfs ref = 32 (3) where iv r ref refio set = / (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , that are tied to analog common, acom. note that r load may represent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly termi nated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply v iouta r outa load = (5) v ioutb r outb load = (6) note that the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain speci- fied distortion and linearity performance. v iouta ioutb r diff load = () ? (7) substituting the values of iouta , ioutb , i ref , and v diff can be expressed as vdac code rrv diff load set refio = () {} () 2 1023 1024 32 ?/ / (8) equations 7 and 8 highlight some of the advantages of operating the ad9740 differentially. first, the differential operation helps cancel common-mode error sources associated with iouta and ioutb, such as noise, distortion, and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the ad9740 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relation- ship, as shown in equation 8. analog outputs the complementary current outputs in each dac, iouta, and ioutb may be configured for single-ended or differential opera- tion. i outa and ioutb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb , can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the ad9740 is optimum and specified using a differential transformer-coupled output in which the voltage swing at iouta and ioutb is limited to 0.5 v. the distortion and noise performance of the ad9740 can be enhanced when it is configured for differential operation. the common-mode error sources of both iouta and ioutb can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more signifi- cant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. this is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a trans- former also provides the ability to deliver twice the reconstructed signal power to the load (assuming no source termination). since the output currents of iouta and ioutb are comple- mentary, they become additive when processed differentially. a properly selected transformer will allow the ad9740 to provide the required power and voltage levels to different loads. the output impedance of iouta and ioutb is determined by the equivalent parallel combination of the pmos switches asso- ciated with the current sources and is typically 100 k w in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining iouta and/or ioutb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note that the inl/dnl specifications for the ad9740 are measured with iouta maintained at a virtual ground via an op amp.
rev. a ?2 ad9740 iouta and ioutb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of ?1 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the ad 9740. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.2 v for an i outfs = 20 ma to 1 v for an i outfs = 2 ma. the optimum distortion performance for a single- ended or differential output is achieved when the maximum full-scale signal at iouta and ioutb does not exceed 0.5 v. digital inputs the ad9740 digital section consists of 10 input bit channels and a clock input. the 10-bit parallel data inputs follow stan- dard positive binary coding, where db9 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. dvdd digital input figure 6. equivalent digital input the digital interface is implemented using an edge-triggered master/slave latch. the dac output updates on the rising edge of the clock and is designed to support a clock rate as high as 165 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transi tion edges may affect digital feedthrough and distortion perfor- mance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. clock input soic/tssop packages the 28-lead package options have a single-ended clock input (clock) that must be driven to rail-to-rail cmos levels. the quality of the dac output is directly related to the clock qual- ity, and jitter is a key concern. any noise or jitter in the clock will translate directly into the dac output. optimal perfor- mance will be achieved if the clock input has a sharp rising edge, since the dac latches are positive edge triggered. lfcsp package a configurable clock input is available in the lfcsp package, which allows for one single-ended and two differential modes. the mode selection is controlled by the cmode input, as summarized in table i. connecting cmode to clkcom selects the single-ended clock input. in this mode, the clk+ input is driven with rail-to-rail swings and the clk? input is left floating. if cmode is connected to clkvdd, the differ- ential receiver mode is selected. in this mode, both inputs are high impedance. the final mode is selected by floating cmode. this mode is also differential, but internal terminations for positive emitter-coupled logic (pecl) are activated. there is no significant performance difference among any of the three clock input modes. table i. clock mode selection cmode pin clock input mode clkcom single-ended clkvdd differential float pecl the single-ended input mode operates in the same way as the clock input in the 28-lead packages, as described previously. in the differential input mode, the clock input functions as a high impedance differential pair. the common-mode level of the clk+ and clk? inputs can vary from 0.75 v to 2.25 v, and the differential voltage can be as low as 0.5 v p-p. this mode can be used to drive the clock with a differential sine wave since the high gain bandwidth of the differential inputs will convert the sine wave into a single-ended square wave internally. the final clock mode allows for a reduced external component count when the dac clock is distributed on the board using pecl logic. the internal termination configuration is shown in figure 7. these termination resistors are untrimmed and can vary up to 20%. however, matching between these resistors should generally be better than 1%. clk+ to dac core clk? v tt = 1.3v nom 50 50 ad9740 clock receiver figure 7. clock termination in pecl mode dac timing input clock and data timing relationship dynamic performance in a dac is dependent on the relation- ship between the position of the clock edges and the time at
rev. a ad9740 ?3 which the input data changes. the ad9740 is rising edge trig- gered, and so exhibits dynamic performance sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9740 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 8 shows the relationship of sfdr to clock placement with different sample rates. note that at the lower sample rates, more tolerance is allowed in clock place- ment, while at higher rates, more care must be taken. ? ? 2 ? 0 1 65 75 ns db 3 55 45 35 60 70 50 40 50mhz sfdr 20mhz sfdr 50mhz sfdr figure 8. sfdr vs. clock placement @ f out = 20 mhz and 50 mhz (f clock = 165 msps) sleep mode operation the ad9740 has a power-down function that turns off the output current and reduces the supply current to less than 6 ma over the specified supply range of 2.7 v to 3.6 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 avdd. this digital input also contains an active pull- down circuit that ensures that the ad9740 remains enabled if this input is left disconnected. the ad9740 takes less than 50 ns to power down and approximately 5 s to power back up. power dissipation the power dissipation, p d , of the ad9740 is dependent on several factors that include: the power supply voltages (avdd, clkvdd, and dvdd) the full-scale current output i outfs the update rate f clock the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in figure 9, and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input waveform, f clock , and digital supply dvdd. figure 10 shows i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 3.3 v. i outfs (ma) 35 0 2 i av d d (ma) 30 25 20 15 10 46810 12 14 16 18 20 figure 9. i avdd vs. i outfs ratio ( f out / f clock ) 16 0.01 1 0.1 i dvdd (ma) 14 12 10 8 6 4 2 0 165msps 125msps 65msps figure 10. i dvdd vs. ratio @ dvdd = 3.3 v 030 150 60 90 120 0 1 2 3 4 5 6 7 8 9 10 f clock (msps) i clkvdd (ma) diff pecl se figure 11. i clkvdd vs. f clock and clock mode
rev. a ?4 ad9740 applying the ad9740 output configurations the following sections illustrate some typical output configura- tions for the ad9740. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications re quiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high frequency performance and is recommended for any application that allows ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb is connected to an appropri ately sized load resistor, r load , referred to acom. this configu- ration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alterna tively, an amplifier could be configured as an i-v converter, thus convert- ing iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 12. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer s pass band. an rf transformer, such as the mini-circuits t1 C 1t, provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9740 mini-circuits t1?t optional r diff iouta ioutb figure 12. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9740. a differential resistor, r diff , may be inserted in applications w here the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformer s impedance ratio and provides the proper source termination that results in a low vswr. note that ap proxi- mately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion, as shown in figure 13. the ad9740 is configured with two equal load resistors, r load , of 25 w . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb, forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amp s dis tortion performance by preventing the dac s high slewing output from overloading the op amp s input. ad9740 iouta ioutb c opt 500 225 225 500 25 25 ad8047 figure 13. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate off a dual supply since its output is approximately 1 v. a high speed amplifier capable of preserving the differential performance of the ad9740 while meeting other system level objectives (e.g., cost or power) should be selected. the op amp s differential gain, gain setting resistor values, and full-scale output swing capabili- ties should all be considered when optimizing this circuit. the differential circuit shown in figure 14 provides the necessary level shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9740 and the op amp, is also used to level shift the differential output of the ad9740 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9740 iouta ioutb c opt 500 225 225 1k 25 25 ad8041 1k avdd figure 14. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 15 shows the ad9740 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly termi- nated 50 w cable, since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 w . in this case, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as
rev. a ad9740 ?5 the positive compliance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl), discussed in the analog output section. for optimum inl performance, the single-ended, buffered voltage output configu- ration is suggested. ad9740 iouta ioutb 50 25 50 v outa = 0v to 0.5v i outfs = 20ma figure 15. 0 v to 0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 16 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the ad9740 output current. u1 maintains iouta (or ioutb) at a virtual ground, minimizing the nonlinear output impedance effect on the dac s inl performance as described in the analog output sec- tion. a lthough this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1 s slew rate capabilities. u1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1 s voltage output swing capabilities by scaling ioutfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since u1 will be required to sink less signal current. ad9740 iouta ioutb c opt 200 u1 v out = i outfs r fb i outfs = 10ma r fb 200 figure 16. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these application cir cuits, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf tech niques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. figures 21 to 24 illustrate the recommended printed circuit board ground, power, and signal plane layouts im ple- mented on the ad9740 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio (psrr). for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dac s full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is gen- erated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. the psrr versus frequency of the ad9740 avdd supply over this frequency range is shown in figure 17. frequency (mhz) 85 40 12 6 0 psrr (db) 80 75 70 65 60 55 50 24 810 45 figure 17. power supply rejection ratio (psrr) note that the ratio in figure 17 is calculated as amps out/volts in. noise on the analog power supply has the effect of modulat- ing the internal switches, and therefore the output current. the voltage noise on avdd, therefore, will be added in a nonlinear manner to the desired iout. due to the relative size of these switches, the psrr is very code dependent. this can pro duce a mixing effect that can modulate low-frequency power supply noise to higher frequencies. worst-case psrr for either one of the differential dac outputs will occur when the full-scale current is directed toward that output. as a result, the psrr measure- ment in figure 17 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switch- ing frequency of 250 khz produces 10 mv of noise and, for simplicity s sake (ignoring harmonics), all of this noise is con- centrated at 250 khz. to calculate how much of this undesired noise will appear as current noise superimposed on the dac s full-scale current, i outfs , one must determine the psrr in db using figure 17 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 17 by the scaling factor 20 log (r load ). for instance, if r load is 50 w , the psrr is re duced by 34 db (i.e., psrr of the dac at 250 khz, which is 85 db in figure 17, becomes 51 db v out /v in ). proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9740 features separate analog and digital supplies and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physically
rev. a ?6 ad9740 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp5 opt 1 dcom 16 1 rp3 22 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db13x db12x db11x db10x db9x db8x db7x db6x db5x db4x db3x db2x db1x db0x 15 2 rp3 22 14 3 rp3 22 13 4 rp3 22 12 5 rp3 22 11 6 rp3 22 10 7 rp3 22 9 8 rp3 22 16 1 rp4 22 15 2 rp4 22 14 3 rp4 22 13 4 rp4 22 12 5 rp4 22 11 6 rp4 22 9 8 rp4 22 10 7 rp4 22 ckext ckextx 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp6 opt 1 dcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp1 opt 1 dcom 2 r1 3 r2 4 r3 5 r4 6 r5 7 r6 8 r7 9 r8 10 r9 rp2 opt 1 dcom 21 db13x 4 3 db12x 65 db11x 87 db10x 10 9 db9x 12 11 db8x 14 13 db7x 16 15 db6x 18 17 db5x 20 19 db4x 22 21 db3x 24 23 db2x 26 25 db1x 28 27 db0x 30 29 32 31 34 33 ckextx 36 35 38 37 40 39 jp3 j1 ribbon tb1 1 tb1 2 l2 bead c7 0.1 f tp4 blk + dvdd tp7 c6 0.1 f c4 10 f 25v blk blk tp8 tp2 red tb1 3 tb1 4 l3 bead c9 0.1 f tp6 blk + av d d tp10 c8 0.1 f c5 10 f 25v blk blk tp9 tp5 red figure 19. soic evaluation board?ower supply and digital inputs possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close to the chip as physically possible. for those applications that require a single 3.3 v supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in figure 18. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low esr type electrolytic and tantalum capacitors. 100 f elect. 0.1 f cer. ttl/cmos logic circuits 3.3v power supply ferrite beads avdd acom 10 f?2 f tant. figure 18. differential lc filter for single 3.3 v applications evaluation board general description the txdac family evaluation boards allow for easy setup and testing of any txdac product in the 28-lead soic and lfcsp packages. careful attention to layout and circuit design, com- bined with a prototyping area, allows the user to evaluate the ad9740 easily and effectively in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9740 in various configurations. possible output configurations include transformer coupled, resistor terminated, and single and differ- ential outputs. the digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad9740 with either the internal or external reference or to exercise the power-down feature.
rev. a ad9740 ?7 r6 opt s2 iouta 2 a b jp10 1 3 ix r11 50 c13 opt jp8 iout s3 4 5 6 3 2 1 t1 t1-1t jp9 c12 opt r10 50 s1 ioutb 1 2 3 ab jp11 iy 1 ext 2 3 int ab jp5 ref + + c14 10 f 16v c16 0.1 f c17 0.1 f av d d dvdd ckext db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 av d d c15 10 f 16v c18 0.1 f c19 0.1 f cut under dut jp6 jp4 r5 opt dvdd r4 50 clock s5 clock tp1 wht dvdd av d d dvdd r2 10k jp2 mode tp3 wht ref c2 0.1 f c1 0.1 f c11 0.1 f r1 2k 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 u1 ad9740 sleep tp11 wht r3 10k clock dvdd dcom mode av d d reserved iouta ioutb a com nc fs adj refio reflo sleep db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 av d d figure 20. soic evaluation board?utput signal conditioning
rev. a ?8 ad9740 figure 21. soic evaluation board?rimary side figure 22. soic evaluation board?econdary side
rev. a ad9740 ?9 figure 23. soic evaluation board?round plane figure 24. soic evaluation board?ower plane
rev. a ?0 ad9740 figure 25. soic evaluation board assembly?rimary side figure 26. soic evaluation board assembly?econdary side
rev. a ad9740 ?1 cvdd red tp12 bead tb1 1 tb1 2 c7 0.1 f c9 0.1 f c3 0.1 f blk tp2 tp4 tp6 blk blk c6 0.1 f c8 0.1 f c10 0.1 f c2 10 f 6.3v c4 10 f 6.3v c5 10 f 6.3v l1 dvdd red tp13 bead tb3 1 tb3 2 l2 avdd red tp5 bead tb4 1 tb4 2 l3 j1 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 39 37 35 33 31 29 27 25 23 21 19 17 15 header straight up male no shroud jp3 ckext x ckext ckextx r21 100 r24 100 r25 100 r26 100 r27 100 r28 100 db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db0x db1x db2x db3x db4x db5x db6x db7x db8x db9x db10x db11x db12x db13x db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 22 16 22 15 22 14 22 13 22 12 22 11 22 10 22 9 r20 100 r19 100 r18 100 r17 100 r16 100 r15 100 r4 100 r3 100 1 rp3 2 rp3 3 rp3 4 rp3 5 rp3 6 rp3 7 rp3 8 rp3 1 rp4 2 rp4 3 rp4 4 rp4 5 rp4 6 rp4 7 rp4 8 rp4 figure 27. lfcsp evaluation board schematic?ower supply and digital inputs
rev. a ?2 ad9740 cvdd cvdd db8 db9 db10 db11 clkb db5 dvdd db6 db7 clk db0 db1 db2 db3 db4 db13 db12 iout avdd dvdd cvdd avdd db8 db9 db10 db11 ib fs adj clkb db5 dvdd db6 db7 clk cvdd dcom db0 db1 db2 db3 db4 dcom1 db13 acom1 avdd acom ia refio avdd1 sleep db12 ccom cmode mode cmode mode t1?t t1 jp8 jp9 4 3 2 1 5 6 s3 agnd: 3, 4, 5 r11 50 r10 50 dnp c13 dnp c12 28 25 17 23 21 22 18 19 27 26 24 20 29 30 31 32 c11 0.1 f r1 2k 0.1% r30 10k r29 10k c17 0.1 f c19 0.1 f c32 0.1 f u1 ad9744lfcsp wht tp1 wht tp11 jp1 wht tp3 tp7 wht sleep 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 figure 28. lfcsp evaluation board schematic?utput signal conditioning u4 u4 jp2 agnd: 5 cvdd: 8 4 3 6 cvdd: 8 c35 0.1 f c20 10 f 16v s5 agnd: 3, 4, 5 c34 0.1 f ckext clk clkb r5 120 r2 120 r6 50 cvdd agnd: 5 2 1 7 cvdd figure 29. lfcsp evaluation board schematic?lock input
rev. a ad9740 ?3 figure 30. lfcsp evaluation board layout?rimary side figure 31. lfcsp evaluation board layout?econdary side
rev. a ?4 ad9740 figure 32. lfcsp evaluation board layout?round plane figure 33. lfcsp evaluation board layout?ower plane
rev. a ad9740 ?5 figure 34. lfcsp evaluation board layout assembly?rimary side figure 35. lfcsp evaluation board layout assembly?econdary side
rev. a ?6 ad9740 outline dimensions 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ae coplanarity 0.10 28-lead standard small outline package [soic] wide body (r-28) dimensions shown in millimeters and (inches) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.32 (0.0126) 0.23 (0.0091) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10 32-lead lead frame chip scale package [lfcsp] (cp-32) dimensions shown in millimeters compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 12 max 0.20 ref 0.05 max 0.02 nom coplanarity 0.08 1.00 max 0.65 nom 1.00 0.90 0.80 1 32 8 9 25 24 16 17 bottom view 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq sq 3.25 3.10 2.95 pin 1 indicator 0.60 max 0.60 max seating plane
rev. a ad9740 ?7 revision history location page 5/03?ata sheet changed from rev. 0 to rev. a. added 32-lead lfcsp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to dynamic specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 replaced tpcs 1, 4, 7, and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 edits to functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 edits to digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 added clock input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 added new figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to dac timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 edits to sleep mode operation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to power dissipation section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 renumbered figures 8 C 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 added figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 added figures 27 C 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
c02911?5/03(a) ?8

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